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QuickLogic PolarProTM Data Sheet
* * * * * * Combining Low Power, Performance, Density, and Embedded RAM Device Highlights
Flexible Programmable Logic
* 0.18 m, six layer metal CMOS process * 1.8 V core voltage, 1.8/2.5/3.3 V drive capable I/Os * Up to 202 kilobits of SRAM * Up to 292 I/Os available * Up to one million system gates * Nonvolatile, instant-on * IEEE 1149.1 boundary scan testing compliant * Quadrant-based segmentable clock networks 20 quad clock networks per device 4 quad clock networks per quadrant 1 dedicated clock network per quadrant * Two user Configurable Clock Managers (CCMs)
Very Low Power (VLP) Mode
* QuickLogic PolarPro has a special VLP pin which can enable a low power sleep mode that significantly reduces the overall power consumption of the device. * Enter VLP mode from normal operation in less than 250 s * Exit from VLP mode to normal operation in less than 250 s
Embedded Dual Port SRAM
* Up to eight dual-port 4-kilobit high performance SRAM blocks * Embedded synchronous/asynchronous FIFO controller * Configurable and cascadable aspect ratio
Security Links
There are several security links to disable JTAG access to the device. Programming these optional links completely disables access to the device from the outside world and provides an extra level of design security not possible in SRAM-based FPGAs.
Figure 1: QuickLogic PolarPro Block Diagram
CCM
GPIO DDR/GPIO DDR/GPIO DDR/GPIO DDR/GPIO
Programmable I/O
* Bank programmable drive strength * Bank programmable slew rate control * Independent I/O banks capable of supporting multiple I/O standards in one device * Native support for DDR I/Os * Bank programmable I/O standards: LVTTL, LVCMOS, and LVCMOS18
CCM
GPIO
Embedded RAM Blocks FIFO Controller
GPIO
Fabric
GPIO GPIO
Advanced Clock Network
GPIO
FIFO Controller Embedded RAM Blocks
GPIO GPIO GPIO GPIO GPIO
* Multiple low skew clock networks 1 dedicated global clock network 4 programmable global clock networks
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QuickLogic PolarProTM Data Sheet Rev. A
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Ultra-Low Power FPGA Combining Performance, Density, and Embedded RAM
Table 1: PolarPro Product Family Members Features Max Gates Logic Cells Max I/O RAM Modules FIFO Controllers RAM bits CCMs TFBGA (0.8 mm) Packages TQFP (0.5 mm) LBGA (1.0 mm) QL1P075 75,000 512 172 8 8 36,864 2 196 144 256 QL1P100 100,000 640 188 8 8 36,864 2 196 144 256 QL1P150 150,000 1,536 292 12 12 55,296 2 256, 324 QL1P300 300,000 1,920 302 12 12 55,296 2 256, 324 QL1P600 600,000 4,224 508 22 22 202,752 2 256, 324 QL1P1000 1,000,000 7,680 652 22 22 202,752 2 256, 324
Process Data
QuickLogic PolarPro is fabricated on a 0.18 , six layer metal CMOS process. The core voltage is 1.8 V. The I/O voltage input tolerance and output drive can be set as 1.8 V, 2.5 V, and 3.3 V.
Programmable Logic Architectural Overview
The QuickLogic PolarPro logic cell structure presented in Figure 2 is a single register, multiplexer-based logic cell. It is designed for wide fan-in and multiple, simultaneous output functions. The cell has a high fan-in, fits a wide range of functions with up to 24 simultaneous inputs (including register control lines), and four outputs (three combinatorial and one registered). The high logic capacity and fan-in of the logic cell accommodates many user functions with a single level of logic delay. The QuickLogic PolarPro logic cell can implement: * Two independent 3-input functions * Any 4-input function * 8 to 1 mux function * Independent 2 to 1 mux function * Single dedicated register with clock enable, active high set and reset signals * Direct input selection to the register, which allows combinatorial and register logic to be used separately * Combinatorial logic that can also be configured as an edge-triggered master-slave D flip-flop
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QuickLogic PolarProTM Data Sheet Rev. A
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Figure 2: PolarPro Logic Cell
QDS QST TBS TAB TSL TI TA1 TA2 TB1 TB2 BAB BSL BI BA1 BA2 BB1 BB2 FS F1 F2 QDI QEN QCK QRT
TZ
0 1 0 1
0 1 0 S 1
0 1
CZ
D E
Q
QZ
0 1 0 1
0 R 1
0 1
FZ
RAM Modules
The QuickLogic PolarPro family of devices includes up to eight 4-kilobit of dual-port RAM modules for implementing RAM and FIFO functions as shown in Figure 3. The RAM features include: * Independently configurable read and write data bus widths * Independent read and write clocks * Horizontal and vertical concatenation * Write byte enables * Selectable pipelined or non-pipelined read data
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QuickLogic PolarProTM Data Sheet Rev. A
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Figure 3: 4-Kilobit Dual-Port RAM Block
WD[17:0] WA[8:0] WEN[1:0] WD_SEL WCLK RA[8:0] RD_SEL RCLK
RD[17:0]
Table 2: RAM Interface Signals Signal Name Inputs WD [17:0] WA [8:0] WEN [1:0] WD_SEL WCLK RA [8:0] RD_SEL RCLK RD [17:0] Write Data Write Address Write Enable (two 9-bit enables) Write Chip Select Write Clock Read Address Read Chip Select Read Clock Output Read Data Function
The read and write data buses of a RAM block can be arranged to variable bus widths. The bus widths can be configured using the RAM Wizard available in QuickWorks, QuickLogic's development software. The selection of the RAM depth and width determines how the data is addressed. The RAM blocks also support data concatenation. Designers can cascade multiple RAM modules to increase the depth or width by connecting corresponding address lines together and dividing the words between modules. Generally, this requires the use of additional programmable logic resources. However, when concatenating only two 4-kilobit RAM blocks, they can be concatenated horizontally or vertically without using any additional programmable fabric resources. For example, two internal dual-port RAM blocks concatenated vertically to create a 512x18 RAM block or horizontally to create a 256x36 RAM block. A block diagram of horizontal and vertical concatenation is displayed in Figure 4.
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QuickLogic PolarProTM Data Sheet Rev. A
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Figure 4: Horizontal and Vertical Concatenation Examples
256x36 Dual-Port RAM
512x18 Dual-Port RAM
WD[35:0] WA[7:0] WEN[3:0] WD_SEL WCLK RA[7:0] RD_SEL RCLK
RD[35:0]
WD[17:0] WA[8:0] WEN[1:0] WD_SEL WCLK RA[8:0] RD_SEL RCLK
RD[17:0]
Horizontal Concatenation
Vertical Concatenation
Table 3 shows the various RAM configurations supported by the PolarPro RAM modules.
Table 3: Available Dual-Port RAM Configurations Number of RAM Blocks 1 1 2 2 2 Depth 256 512 256 512 1024 Width 1 to 18 1 to 9 1 to 36 1 to 18 1 to 9
True Dual-Port RAM
PolarPro dual-port RAM modules can also be concatenated to generate true dual-port RAMs. The true dualport RAM module's Port1 and Port2 have completely independent read and write ports, and separate read and write clocks. This allows Port1 and Port2 to have different data widths and clock domains. It is important to note that there is no circuitry preventing a write and read operation to the same address space at the same time. Therefore, it is up to the designer to ensure that the same address is not read from and written to simultaneously, otherwise the data is considered invalid. Likewise, the same address must not be written to from both ports at the same time. However, it is possible to read from the same address. Figure 5 shows an example of a 512x18 true dual-port RAM.
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Figure 5: 512x18 True Dual-Port RAM Block
Port1_WD[17:0] Port1_A[8:0] Port1_WEN Port1_CS Port1_CLK Port2_WD[17:0] Port2_A[8:0] Port2_WEN Port2_CS Port2_CLK
Port1_RD[17:0]
Port2_RD[17:0]
Table 4: True Dual-Port RAM Interface Signals Port Signal Name Inputs Port1_WD[17:0] Port1_A[8:0] Port1 Port1_WEN Port1_CS Port1_CLK Output Port1_RD[17:0] Inputs Port2_WD[17:0] Port2_A[8:0] Port2 Port2_WEN Port2_CS Port2_CLK Output Port2_RD[17:0] Read Data Write Data Write Address Write Enable Chip Select Clock Read Data Write Data Write Address Write Enable Chip Select Clock Function
Table 5: Available True Dual-Port RAM Configurations Number of RAM Blocks 2 2 Depth 512 1024 Width 1 to 18 1 to 9
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QuickLogic PolarProTM Data Sheet Rev. A
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Embedded FIFO Controllers
Every 4-kilobit RAM block can be implemented as a synchronous or asynchronous FIFO. There are built-in FIFO controllers that allow for varying depths and widths without requiring programmable fabric resources. The PolarPro FIFO controller features include: * x9, x18 and x36 data bus widths * Independent PUSH and POP clocks * Independent programmable data width on PUSH and POP sides * Configurable synchronous or asynchronous FIFO operation * 4-bit PUSH and POP level indicators to provide FIFO status outputs for each port * Pipelined read data to improve timing
Figure 6: FIFO Module
DIN[x:0] PUSH Fifo_Push_Flush Push_Clk POP Fifo_Pop_Flush Pop_Clk
DOUT[x:0]
Almost_Full Almost_Empty PUSH_FLAG[3:0] POP_FLAG[3:0]
NOTE: x = {1,2,3,...35}.
Table 6: Available FIFO Configurations Number of RAM Blocks Used 1 1 2 2 2 Depth 256 512 256 512 1024 Supported Widths 1 to 18 bits 1 to 9 bits 1 to 36 bits 1 to 18 bits 1 to 9 bits
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QuickLogic PolarProTM Data Sheet Rev. A
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Table 7 lists the FIFO controller interface signals.
Table 7: FIFO Interface Signals Signal Name DIN PUSH Fifo_Push_Flush Push_Clk DOUT POP Fifo_Pop_Flush Pop_Clk Almost_Full Almost_Empty PUSH_FLAG[3:0] POP_FLAG[3:0] Width (bits) 1 to 36 1 1 1 1 to 36 1 1 1 1 1 4 4 Direction PUSH Signals I I I I O I I I O O O O Data bus input Initiates a data push Empties the FIFO Push data clock Data bus output Initiates a data pop Empties the FIFO Pop data clock Asserted when FIFO has one location available Asserted when FIFO has one location used FIFO PUSH level indicator FIFO POP level indicator Function
POP Signals
Status Flags
Table 8 and Table 9 highlight the corresponding FIFO level indicator for each 4-bit value of the PUSH_FLAG and POP_FLAG outputs.
Table 8: FIFO PUSH Level Indicator Values Value 0000 0001 0010 0011 1000 1001 1010 1011 1100 1101 1110 1111 Others Full Empty Room for more than one-half Room for more than one-forth Room for 8 or more Room for 7 Room for 6 Room for 5 Room for 4 Room for 3 Room for 2 Room for 1 Reserved Status
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QuickLogic PolarProTM Data Sheet Rev. A
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Table 9: FIFO POP Level Interface Signals Value 0000 0001 0010 0011 1000 1010 1100 1110 1000 1101 1110 1111 Others Empty 1 entry in FIFO 2 entries in FIFO 3 entries in FIFO 4 entries in FIFO 5 entries in FIFO 6 entries in FIFO 7 entries in FIFO 8 or more entries in FIFO One-forth or more full One-half or more full Full Reserved Status
FIFO Flush Procedure
Both PUSH and POP domains are provided with a flush input signal synchronized to their respective clocks. When a flush is triggered from one side of the FIFO, the signal propagates and re-synchronizes internally to the other clock domain. During a flush operation, the values of the FIFO flags are invalid for a specific number of cycles (see Figure 7 and Figure 8). As shown in Figure 7, when the Fifo_Push_Flush asserts, the Almost_Full and PUSH_FLAG signals become invalid until the FIFO can flush the data with regards to the Push clock domain as well as the Pop clock domain. After the Fifo_Push_Flush is asserted, the next rising edge of the Pop clock starts the Pop flush routine. Figure 7 illustrates a FIFO Flush operation. After the Fifo_Push_Flush is asserted at 2 (PUSH_Clk), four POP clock cycles (12 through 15) are required to update the POP_FLAG, and PUSH_FLAG signals. The Almost_Empty signal is asserted to indicate that the push flush operation has been completed. On the following rising edge of the PUSH_Clk (8), the PUSH_FLAG is accordingly updated to reflect the successful flush operation.
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Figure 7: FIFO Flush from PUSH Side
earliest PUSH
1
2
3
4
5
6
7
8
9
10
PUSH_Clk Fifo_Push_Flush Almost_Full PUSH_FLAG POP_Clk Almost_Empty POP_FLAG
valid invalid 0000 (Empty) valid
11 12 13
invalid
invalid
14 15
valid
16
Figure 8 illustrates a POP flush operation. After the Fifo_Pop_Flush is asserted at 2 (POP_Clk), four PUSH clock cycles (12 through 15) are required to update the POP_FLAG, and PUSH_FLAG signals. The Almost_Empty signal is asserted to indicate that the pop flush operation has been completed. On the following rising edge of the POP_Clk (8), the POP_FLAG is updated accordingly to reflect the successful flush operation.
Figure 8: FIFO Flush from POP Side
earliest P U S H
1 2 3 4 5 6 7 8 9 10
P O P _C lk Fifo_P op_Flush A lm ost_E m pty P O P _FLA G
11
valid
invalid
0000 (E m pty)
12
13
14
15
16
P U S H _C lk A lm ost_Full P U S H _FLA G
valid invalid invalid valid
Figure 7 and Figure 8 are only true for this particular PUSH-POP clock frequency combination. The clock frequency and phase difference between POP_Clk and PUSH_Clk can cause an additional flush delay of one clock cycle in either domain because of the asynchronous relationship between the two clocks.
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QuickLogic PolarProTM Data Sheet Rev. A
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Distributed Clock Networks
Global Clocks
The PolarPro clock network architecture consists of a 2-level H-tree network as shown in Figure 9. The first level of each clock tree (high-lighted in red) spans from the clock input pad to the global clock network and to the center of each quadrant of the chip. The second level (high-lighted in blue) spans from the quadrant clock network to every logic cell inside that quadrant. There are five global clocks in the global clock network, and five quadrant clocks in each quadrant clock network. All global clocks drive the quadrant clock network inputs. The quadrant clocks output to clock inversion muxes, which pass either the original input clock or an inverted version of the input clock to the logic cells in that quadrant. The clock networks can drive RAM block clock inputs and reset, set, enable, and clock inputs to I/O registers. Furthermore, the quadrant clock outputs can be routed to all logic cell inputs.
Figure 9: Global Clock Architecture
x4
Quadrant Clock Network
Inversion Mux
Quadrant Clock x4 Network
Global Clock Network x4
x4 Quadrant Clock Network
x4 Quadrant Clock Network
Of the five global clock networks, four can be either driven directly by clock pads, Configurable Clock Manager (CCM) outputs, or internally generated signals. These four clock nets go through 3-input global clock muxes located in the middle of the die. See Figure 10 for a diagram of a 3-input global clock mux. The fifth is a dedicated global clock network that goes directly to the quadrant quad-net clock network and is used as a dedicated fast clock.
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Figure 10: Global Clock Structure
C C M output Internally generated clock, or cloc k from general routing network
T o Quadrant C loc k S tructure
G lobal C loc k (C LK ) Input P ad
2-bit s elect G lobal C loc k B uffer
Figure 11 illustrates the quadrant clock 2-input mux.
Figure 11: Quadrant Clock Structure
T o invers ion mux, then logic cells F rom G lobal clock buffer Logic C ell
Internally generated clock, or cloc k from general routing network
1-bit s elect Quadrant C loc k B uffer
It is important to note that the select lines for the global clock and quad-net muxes are static signals and cannot be changed dynamically during device operation. For more information about global and quad-net clock networks and how to use them, refer to Application Note 85 Clock Networks in PolarPro Devices at http://www.quicklogic.com/images/appnote85.pdf.
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QuickLogic PolarProTM Data Sheet Rev. A
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Configurable Clock Managers
The CCM features include: * Input frequency range from 25 MHz to 150 MHz * Output frequency range from 25 MHz to 300 MHz * Output jitter is less than 200 ps * Two outputs: pullout0 (with 0 phase shift), and pullout1 (with an option of 0, 90, 180, or 270 phase shift plus a programmable delay). * Programmable delay allows delays up to 2.5 ns at 250 ps intervals * CCM inputs can be driven from either a clock input pad or internal routing * Programmable or fixed feedback path
Figure 12: Configurable Clock Manager
ded_in ded_in pgm_in pgm_in fin_cnt fin_cnt ded_fd ded_fd pgm_fd pgm_fd fd_cnt fd_cnt rst_in rst_in fc[1:0] fc[1:0] s[1:0] s[1:0] tdctl[3:0] tdctl[3:0]
pllout0 pllout0 pllout1 pllout1 lock_out lock_out
The reset signal can be routed from a clock pad or generated using internal logic. The lock_out signal can be routed to internal logic and/or an output pad. Both CCM clock outputs can drive the global clock networks, as well as any general purpose I/O pin. Once the CCM has synchronized the output clock to the incoming clock, the lock_out signal will be asserted to indicate that the output clock is valid. Lock detection requires at least 2 s after reset to assert lock_out. The PolarPro CCMs have three modes of operation, based on the input frequency and desired output frequency. Table 10 indicates the features of each mode.
Table 10: CCM PLL Mode Frequencies Output Frequency x1 x2 x4 Input Frequency Range 25 MHz to150 MHz 25 MHz to 150 MHz 25 MHz to 75 MHz Output Frequency Range 25 MHz to 150 MHz 50 MHz to 300 MHz 100 MHz to 300 MHz PLL Mode PLL_MULT1 PLL_MULT2 PLL_MULT4
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CCM Signals
Table 11 provides the name, direction, function and description of the CCM ports.
Table 11: CCM Signals Signal Name ded_in pgm_in ded_fd pgm_fd rst_in pllout0 pllout1 lock_out Direction I I I I I O O O Function Routable Ports Dedicated Input Programmable Input Dedicated Feedback Clock pad CCM input source. Internal logic CCM input source. Automatically calculated and routed by the software tools. Active high reset: If rst_in is asserted, pllout0 and pllout1 are reset to 0. This signal must be asserted and then released for lock_out to assert. 0 phase clock output. 0, 90,180, or 270 phase clock output with programmable delay. Active high lock detection signal. Active when the pllout signals correctly output the configured functionality. Static Ports fin_cnt fd_cnt fc[1:0] s[1:0] I I I I Clock Input Control Feedback Control Phase Shift Control Set Mode Mux signal that selects between the dedicated or programmable clock input. Mux signal that selects between the dedicated or programmable feedback input. Determines whether pllout1 is 0, 90, 180, or 270 degrees out of phase with pllout0. Determines pllout1 and pllout0 frequency multiplier (x1, x2, or x4). Pllout1 programmable delay, configurable in 250 ps increments up to a maximum of 2.5 ns. NOTE: 205 ps can vary depending on process variation. Description
Programmable Feedback Routed from internal logic. Configured by the user. Reset 0 Phase Clock Configurable Phase Clock Lock Detect
tdctl[3:0]
I
Time Delay Control
Table 12, Table 13, and Table 14 give the values used to configure the Set Mode, Phase Shift Control and Time Delay Control bits.
Table 12: Set Mode Values pllout0/ pllout1 00 01 10 11 Multiplier x1 x2 x4 Reserved
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QuickLogic PolarProTM Data Sheet Rev. A
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Table 13: Phase Shift Control Values fc[1:0] 00 01 10 11 Phase Shift (Deg.) 0 90 180 270
Table 14: Time Delay Control Values tdctl[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Time Delay (ps) 0 250 500 750 1000 1250 1500 1750 2000 2250 2500 Reserved Reserved Reserved Reserved Reserved
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CCM Configurations
The main purpose of the CCM is to align the clock arrival times of two separate clock destinations, whether it is within the FPGA or external to the chip. The difference between the two clock destinations is referred to as clock skew. To correct for clock skew the CCMs can be configured to shift the phase and/or delay of the pllout1 clock output. In most cases the desired phase or added delay can be accomplished by configuring both the clock source input and feedback input as dedicated. In the case of a dedicated clock source and dedicated feedback, the QuickLogic development software calculates and generates all of the required routing delays to produce the requested configuration. However, if a more specific delay is required, the programmable feedback path can be configured to generate the desired pllout0 and pllout1 output. To accomplish this task the relationship between the CCM input clock source and feedback path must be understood. Specifically, the delay from the clock source to the CCM input, the delay from the CCM to the destination, and the delay from the destination to the CCM feedback input must all be taken into account. For the purpose of this document these delays are defined as: A = Delay from the source clock or clock I/O pad to the input of the CCM B = Delay from the output of the CCM to the destination logic element C = Delay from internal or external destination to the CCM Figure 13 shows a representation of the corresponding delays. In Figure 13 the combination of the various delays associated from one location to another are graphically represented by a single buffer.
Figure 13: CCM Routing
A
Clock Source
CCM
clock input pllout0
B
feedback input
Destination Logic Element
DC
note: clock input can be ded_in or pgm_in feedback input can be ded_fb or pgm_fb
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QuickLogic PolarProTM Data Sheet Rev. A
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Table 15: Available Configurations CCM Case 1 Clock Dedicated clock pad Dedicated clock pad Feedback Dedicated feedback Programmable feedback from logic Programmable feedback from I/O Example Usage Standard PLL application. Reduce set-up and hold time requirements. Generate an early or late clock (in regards to the clock input pad) to remove skew, or synchronize arrival times. Reduce FPGA or external component delays (set-up and hold times) Comments If the clock pad and destination are in phase, then A = C If C > A, pllout0 = early clock If C < A, pllout0 = late clock pllout will drive out through an I/O pad and connect back to the feedback pad. If C > A, pllout0 = early clock If C < A, pllout0 = late clock 4 Programmable Programmable input from feedback from logic or I/O logic Programmable Programmable input from feedback from logic or I/O I/O Clock signal manipulation on internally derived clocks. Operate on clock signal internally or externally. Useful for clock derivation.
2
Dedicated clock pad 3
5
Requires knowledge of off-chip delays.
For more information on CCMs and how to use them in QuickWorks, refer to Application Note 87 Configurable Clock Managers at http://www.quicklogic.com/images/appnote87.pdf.
General Purpose Input Output (GPIO) Cell Structure
The GPIO features include: * Direct or registered input with input path select * Direct or registered output with output path select * Direct or registered output enable with OE path select * Input buffer enable to reduce power * Programmable weak keeper, programmable pull-up/pull-down control * Programmable drive strength * Configurable slew rate * Support for JTAG boundary scan
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QuickLogic PolarProTM Data Sheet Rev. A
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Figure 14: PolarPro GPIO Cell
SLEW[1:0] P[3:0]
I/O PAD
OUTZ OUTRZ_EN D Q Slew Rate & Drive Strength Logic
OSEL
OEZ
D
Q
ESEL
INZ Q ISEL D FIXHOLD logic
INRZ_EN FIXHOLD RST CLK DI_EN PBE PBD PBK
weak pull-up/pull-down controller
With bi-directional I/O pins and global clock input pins, the PolarPro device maximizes I/O performance, functionality, and flexibility. All input and I/O pins are 1.8 V, 2.5 V, and 3.3 V tolerant and comply with the specific I/O standard selected. For single-ended I/O standards, the corresponding VCCIO bank input specifies the input tolerance and the output drive voltage. Drive strength and slew rate are configured for an entire bank. Weak keeper, pull-up, and pull-down functions can be configured for individual I/O.
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QuickLogic PolarProTM Data Sheet Rev. A
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Table 16: GPIO Interface Signals Signal Name OUTZ OUTRZ_EN OEZ INZ INRZ_EN RST CLK DI_EN Direction Routable Signals I I I O I I I I Data out from internal logic Enable for registered OUTZ Tristate enable for the output signal Input signal to the internal logic Enable for registered INZ Reset for optional registers Clock signal for optional registers Enable for I/O input signal. Drives a 1 to internal logic when disabled. Static Signals SLEW[1:0] P[3:0] OSEL ESEL ISEL FIXHOLD PBE PBD PBK I I I I I I I I I Input signals for the weak keeper, pull-up/pull-down controller, see Table 17 for functional behavior 2-bit slew rate control Programmable drive strength Select signal for registered or flow through OUTZ Select signal for registered or flow-through OEZ Select signal for registered or flow-through INZ Enable control for I/O input delay for hold fixing Function
Programmable Weak Keeper, Pull-Up, and Pull-Down
A programmable Weak Keeper, Pull-Up or Pull-Down controller is also available on each General Purpose I/O bank. When implementing the Weak Keeper, Pull-Up, and Pull-Down functions, each I/O can be configured separately. The I/O Weak Pull-Up and Pull-Down eliminates the need for external resistors. When PBK=1 the keeper block is placed into keeper mode. In the keeper mode, the pad pin (if the driver is tristated), will be kept at whichever level it was last forced, either by the driver itself, or by an external driver.
Table 17: Weak Pull-Up, and Pull-Down Controller PBK 0 0 0 1 0 PBD 0 0 1 X 1 PBE 0 1 1 X 0 Function Tristate (floating) Weak Pull-Down Weak Pull-Up Weak Keeper (retains state) Reserved
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Programmable Drive Strength
Table 18 lists the worst case process (TJ=125xC) output currents (in mA) across the output driver at three levels of I/O voltages. The GPIO output current drive strength is guaranteed to be the specified amount in Table 18 or better.
Table 18: Programmable Drive Strength P[3:0] 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1111 Others Drive Strength x1 x2 x3 x4 x5 x6 x7 x8 x9 x10 x11 x12 N/A Worst Case Output Current (mA) at VCCIO = 1.62 V 1.6 3.2 4.8 6.4 8.0 9.6 11.2 12.8 14.4 16.0 17.8 19.4 2.25 V 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 25.0 27.5 29.0 Reserved 2.97 V 3.1 6.2 9.3 12.4 15.5 18.6 21.7 24.8 27.9 31.0 34.1 35.7
Programmable Slew Rate
Each I/O has programmable slew rate capability. The PolarPro GPIOs allow up to four different slew rate speeds. Slower slew rates can be used to reduce noise caused by I/O switching. Table 19 lists the typical output slew rates (in V/ns) with various levels of output voltages and a load capacitor of 10 pF.
Table 19: Output Slew Rate Control Slew[1:0] 00 01 10 11 Typical Output Slew Rate (V/ns) at VCCIO = 1.8V 0.13 0.25 0.50 1.00 2.5V 0.25 0.50 1.00 2.00 3.3V 0.50 1.00 2.00 4.00
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QuickLogic PolarProTM Data Sheet Rev. A
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I/O interface standards are programmable on a per bank basis. Table 20 illustrates the I/O bank configurations available. Each I/O bank is independent of other I/O banks and each I/O bank has its own VCCIO supply inputs. A mixture of different I/O standards can be used on a PolarPro device. However, there is a limitation as to which I/O standards can be supported within a given bank. Only standards that share a common VCCIO can be shared within the same bank (e.g., PCI and LVTTL).
Table 20: I/O Standards and Applications I/O Standard LVTTL LVCMOS25 LVCMOS18 PCI VCCIO Voltage 3.3 V 2.5 V 1.8 V 3.3 V Application General Purpose General Purpose General Purpose PCI Bus Applications
DDRIO Cell Structure
QuickLogic PolarPro devices support DDRIOs, which allows clocking data on both the positive and negative clock edges. All PolarPro devices have one I/O bank (Bank D) that can be configured in either a GPIO bank or a DDRIO mode. When bank D is configured to DDRIO mode, it is further divided into DDRIO sets. Each set contains 12 I/Os, which include 8 DQs, 1 DQM, 1 DQS, 1 DQCK_N and 1 DQCK_P (for the differential clocks, refer to Table 21).
Figure 15: PolarPro DDRIO Block Diagram
DDR SET4
DDR SET3
DDR SET2
DDR SET1
DQ DQ DQ DQ DQ DQS DQCK_N DQCK_P DQ DQ DQ DQM
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Table 21: Available DDR Sets PolarPro Device Package PF144 QL1P075 PT196 PS256 PF144 QL1P100 PT196 PS324 QL1P150 QL1P300 QL1P600 QL1P1000 PS256 PS324 PS256 PS324 PS256 PS324 PS256 PS324 Number of DDR Sets 2 4 4 2 4 4 4 4 4 4 4 4 4 4
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Double Data Rate (DDR) I/O
The DDR features include: * Programmable slew rate * Programmable drive strength * Programmable pull-up
Figure 16: DDRIO DQ Configuration
DQ DQL/OUTZ DQH OSEL DOI ESEL CLK 270 DDR_EN OEZ
DDR_EN DQLI/INZ DQHI
+ Vref DDR_EN
CLK DDR_EN CLK_SYNC DQS_SHF
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Figure 17: DDRIO DQS Configuration
DQS WRT_EN/ OUTZ DOI CLK
OSEL RESYNCH_ DQ_WR DDR_EN FSEL OEZ RESYNCH_WQ_WR INZ DDR_EN
ISEL + DQS_SHF DQS DELAY Vref
Table 22: DDR DQ Fabric Interface Signals Signal Name DDR_EN CLK270 PDB CLK RST INRZ_EN DQH OUTRZ_EN DQL / OUTZ OEZ DQHI DQLI / INZ Direction Routable Signals I I I I I I I I I I O O Enable DDR function, otherwise function will be that of GPIO. Shifted clock used in center-aligning data with DQS in writing out data. Used as control for differential power-down. System clock signal from the programmable fabric. Reset signal for registers inside the I/O. Enable for registered DQLI / INZ. Higher bit DQ signal output from core. GPIO: enable for registered OUTZ signal. DDR(DQL): lower bit DQ signal output from core. GPIO(OUTZ): data out from core with optional register. Tristate enable for the output signal with optional register. Higher bit DQ signal input to core with optional register for resynchronization. DDR(DQLI): lower bit DQ signal input to core with optional register for resynchronization. GPIO(INZ): data in signal to core with optional register. Function
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Table 22: DDR DQ Fabric Interface Signals (Continued) Signal Name Direction Static Signals resync_DQ_rd resync_DQ_wr SLEW[1:0] P[3:0] N[3:0] FIXHOLD PBE DOI ISEL OSEL ESEL I I I I I I I I I I I Signal to enable resynching of DQ being read to avoid setup violations inside the programmable fabric. Signal to enable resynching of DQ being written to avoid setup violations inside the I/O. 2-bit slew rate control. Pull-up programmable drive strength. Pull-down programmable drive strength. Enable control for I/O input delay for hold fixing. Input signal for weak pull-up controller. Used as control for data out inversion. Select signal for registered or flow through INZ. Select signal for registered or flow through OUTZ. Select signal for registered or flow through OEZ. Function
Table 23: DDR DQS Interface Signals Signal Name Direction Routable Signals CLK_SYNC PDB CLK RST INRZ_EN INZ DQS_BR_REL OEZ OUTRZ_EN WRT_EN I I I I I O I I I I Optional resynchronization clock to sync incoming data with the programmable fabric system clock. Control for differential power-down. System clock signal from the programmable fabric. Reset signal for registers inside the I/O. GPIO: enable for registered INZ. GPIO: data in signal to core with optional register. A read burst signal used to mask the end of DQS pulses to avoid unnecessary glitches that will result in clocking-in unwanted data. Tristate enable for the output signal with optional register. Enable for registered or flow-through WRT_EN/OUTZ. DDR(WRT_EN): write enable signal. GPIO(OUTZ): data out from core with optional register. Static Signals CLK_SYNC_DEL_ CTRL[4:0] CLK_SYNC_INV resync_DQ_wr DDR_EN FIXHOLD I I I I I Setting to program delay for CLK_SYNC. Option to invert CLK_SYNC. Signal to enable resynching of DQ being written to avoid setup violations inside I/O. Enable DDR function, otherwise function will be that of GPIO. Enable control for I/O input delay for hold fixing. Function
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Table 23: DDR DQS Interface Signals (Continued) Signal Name PBE SLEW[1:0] P[3:0] N[3:0] DOI ISEL OSEL ESEL DQS_DEL_ CTRL[3:0] Direction I I I I I I I I I Slew rate control setting. Pull-up programmable drive strength. Pull-down programmable drive strength. Control for data out inversion. DDR: selects between VREF (ISEL=0) or PADI (ISEL=1), to connect to the inverting-input of a differential amplifier inside the DDR I/O driver. GPIO: Select signal for registered or flow-through INZ. Select signal for registered or flow-through WRT_EN/OUTZ. Select signal for registered or flow-through DQS_OE/OEZ. Setting to program delay of DQS signal. Function Input signal for weak pull-up controller.
Very Low Power Mode
The QuickLogic PolarPro devices have a unique feature, referred to as VLP mode, which reduces power consumption by placing the device in standby. Specifically, VLP mode can bring the total standby current down to less than 10 A at room temperature when no incoming signals are toggled. VLP mode is controlled by the VLP pin. The VLP pin is active low, so VLP mode is activated by pulling the VLP pin to ground. Conversely, the VLP pin must be pulled to 3.3 V for normal operation. When a PolarPro device goes into VLP mode, the following occurs: * All logic cell registers and GPIO registers values are held * All RAM cell data is retained * The outputs from all GPIO to the internal logic are tied to a weak `1' * GPIO outputs drive the previous values * GPIO output enables retain the previous values * DDRIO outputs are pulled down through a weak pull down circuit * Clock pad inputs are gated * CCMs are held in the reset state The entire operation from normal mode to VLP mode requires 250s. Since the output of the GPIO to the internal logic is a weak `1', the GPIO should not be used to drive any asynchronous active high signal, like set or reset. If the GPIO is an active high set or reset, then the registers may be cleared or set prior to entering VLP mode, hence replacing the previous register values. As the device exits out of VLP mode, the data from the registers, RAM, and GPIO will be used to recover the functionality of the device. Furthermore, since the CCMs were in a reset state during VLP mode, they will have to re-acquire the correct output signals before asserting lock_out. The time required to go from VLP mode to normal operation is 250 s. Figure 18 displays the delays associated with entering and exiting VLP mode.
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Figure 18: VLP Mode Timing
VLP pin 250us VLP status VLP inactive VLP mode 250us
Normal Operation
VLP inactive
Joint Test Access Group (JTAG) Information
Figure 19: JTAG Block Diagram
TCK TMS TRSTB
Tap Controller State Machine (16 States)
Instruction Decode & Control Logic
Instruction Register
RDI
Mux Boundary-Scan Register (Data Register)
Mux
TDO
Bypass Register
Internal Register
I/O Registers
User Defined Data Register
QuickLogic's PolarPro family complies with IEEE standard 1149.1, the Standard Test Access Port and Boundary Scan Architecture. The JTAG boundary scan test methodology allows complete observation and control of the boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP) controller works in concert with the Instruction Register (IR), which allow users to run three required tests along with several user-defined tests. JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse subsystem tests for comprehensive verification of higher level system elements.
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The 1149.1 standard requires the following three tests: * Extest Instruction. The Extest Instruction performs a printed circuit board (PCB) interconnect test. This test places a device into an external boundary test mode, selecting the boundary scan register to be connected between the TAP Test Data In (TDI) and Test Data Out (TDO) pins. Boundary scan cells are preloaded with test patterns (through the Sample/Preload Instruction), and input boundary cells capture the input data for analysis. * Sample/Preload Instruction. The Sample/Preload Instruction allows a device to remain in its functional mode, while selecting the boundary scan register to be connected between the TDI and TDO pins. For this test, the boundary scan register can be accessed through a data scan operation, allowing users to sample the functional data entering and leaving the device. * Bypass Instruction. The Bypass Instruction allows data to skip a device boundary scan entirely, so the data passes through the bypass register. The Bypass instruction allows users to test a device without passing through other devices. The bypass register is connected between the TDI and TDO pins, allowing serial data to be transferred through a device without affecting the operation of the device.
JTAG BSDL Support
* Boundary Scan Description Language (BSDL) * Machine-readable data for test equipment to generate testing vectors and software * BSDL files available for all device/package combinations from QuickLogic * Extensive industry support available and ATVG (Automatic Test Vector Generation)
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Electrical Specifications
DC Characteristics
The DC Specifications are provided in Table 24 through Table 27. Table 24: Absolute Maximum Ratings
Parameter VCC Voltage VCCIO Voltage VREF Voltage Input Voltage Value -0.5 V to 2.0 V -0.5 V to 4.0 V 0.5 V to VCCIO -0.5 V to VCCIO + 0.5 V Parameter Latch-up Immunity ESD Pad Protection Leaded Package Storage Temperature Laminate Package (BGA) Storage Temperature -65 C to + 150 C -55 C to + 125 C Value 100 mA
Table 25: Recommended Operating Range
Symbol VCC VCCIO TJ K Parameter Supply Voltage I/O Input Tolerance Voltage Junction Temperature -6 Speed Grade Delay Factor -7 Speed Grade -8 Speed Grade Military Min. 1.71 1.71 -55 0.49 0.48 0.45 Max. 1.89 3.60 125 1.57 1.40 1.32 Industrial Min. 1.71 1.71 -40 0.50 0.50 0.47 Max. 1.89 3.60 100 1.51 1.34 1.26 Commercial Min. 1.71 1.71 0 0.54 0.53 0.50 Max. 1.89 3.60 85 1.47 1.31 1.23 Unit V V C n/a n/a n/a
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NOTE: VI characteristics, drive current, and quiescent current data will be supplied once characterization has been completed. Table 26: DC Characteristics
Symbol Il IOZ CI CCLOCK IOS IREF IPD IPLL IVCCIO Parameter I or I/O Input Leakage Current 3-State Output Leakage Current I/O Input Capacitance Clock Input Capacitance Output Short Circuit Currenta Quiescent Current on VREF Current on programmable pull-down Quiescent Current on each VCCPLL Conditions VI = VCCIO or GND VI = VCCIO or GND VO = GND VO = VCC VCC = 1.8 V 2.5 V 3.3 V VCCIO = 3.6 V VCCIO = 2.5 V VCCIO = 1.8 V Min. -1 -15 40 -10 Max. 1 1 8 8 -180 210 10 50 3 20 10 10 Units A A pF pF mA mA A A mA
Quiescent Current on VCCIO
-
A
a. The data provided in Table 26 represents the JEDEC and PCI specifications.
Table 27: DC Input and Output Levelsa
Symbol LVTTL LVCMOS2 LVCMOS18 GTL+ PCI SSTL2 SSTL3 INREF VMIN VMAX VMIN n/a n/a n/a 0.88 n/a 1.15 1.3 n/a n/a n/a 1.12 n/a 1.35 1.7 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 VIL VMAX 0.8 0.7 0.63 INREF - 0.2 0.3 x VCCIO INREF - 0.2 VMIN 2.2 1.7 1.2 INREF + 0.2 0.6 x VCCIO INREF + 0.2 VIH VMAX VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VCCIO + 0.3 VOL VMAX 0.4 0.7 0.7 0.6 0.74 1.10 VOH VMIN 2.4 1.7 1.7 n/a 1.76 1.90 IOL mA 2.0 2.0 2.0 40 7.6 8 IOH mA -2.0 -2.0 -2.0 n/a -0.5 -7.6 -8
VCCIO + 0.5 0.1 x VCCIO 0.9 x VCCIO 1.5 VCCIO + 0.3
-0.3 INREF - 0.18 INREF + 0.18 VCCIO + 0.3
a. The data provided in Table 27 represents the JEDEC and PCI specification. QuickLogic devices either meet or exceed these requirements.
NOTE: All CLK and CCM pins are clamped to the VCC rail. Therefore, these pins can be driven up to VCC. All JTAG inputs are clamped to the VCC rail. These JTAG input pins can only be driven up to VCC.
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AC Characteristics
NOTE: The AC specifications will be provided in Table 28 through Table 38 once production silicon has been characterized. Logic cell diagrams and waveforms are provided in Figure 20 through Figure 33.
Figure 20: PolarPro Logic Cell
QDS QST TBS TAB TSL TI TA1 TA2 TB1 TB2 BAB BSL BI BA1 BA2 BB1 BB2 FS F1 F2 QDI QEN QCK QRT
TZ
0 1 0 1
0 1 0 S 1
0 1
CZ
D E
Q
QZ
0 1 0 1
0 R 1
0 1
FZ
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Table 28: Logic Cell Delays
Symbol tPD tSU tHL tCO tCWHI tCWLO tSET tRESET tSW tRW Parameter Combinatorial Delay of the longest path: time taken by the combinatorial circuit to output Setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Clock-to-out delay: the amount of time taken by the flip-flop to output after the active clock edge. Clock High Time: required minimum time the clock stays high Clock Low Time: required minimum time that the clock stays low Set Delay: time between when the flip-flop is "set" (high) and when the output is consequently "set" (high) Reset Delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Set Width: time that the SET signal must remain high/low Reset Width: time that the RESET signal must remain high/low Figure 21: Logic Cell Flip-Flop Timings--First Waveform Value Min. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
CLK
tCWHI (min)
QDS (set) QRT (reset)
tCWLO (min)
Q
tRESET tRW
tSET tSW
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Figure 22: Logic Cell Flip-Flop Timings--Second Waveform
CLK
D
tSU
Q
tHL
tCO
Figure 23: PolarPro Clock Network
x4
Quadrant Clock Network
Inversion Mux
Quadrant Clock Network x4
Global Clock Network x4
x4 Quadrant Clock Network
x4 Quadrant Clock Network
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Table 29: PolarPro Clock Network Delay
Clock Segment tPGCK tBGCK tDPD tGSKEW tDSKEW Parameter Global clock pin delay to quad net Global clock tree delay (quad net to flip-flop) Dedicated clock pad Global delay clock skew Dedicated clock skew Value Min. TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD
RAM Timing
Figure 24: RAM Module
WD[17:0] WA[8:0] WEN[1:0] WD_SEL WCLK RA[8:0] RD_SEL RCLK
RD[17:0]
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Table 30: RAM Cell Write Timing
Symbol RAM Cell Synchronous Write Timing tSWA tHWA tSWD tHWD tSWE tHWE tWCRD WA setup time to WCLK: time the WRITE ADDRESS must be stable before the active edge of the WRITE CLOCK WA hold time to WCLK: time the WRITE ADDRESS must be stable after the active edge of the WRITE CLOCK WD setup time to WCLK: time the WRITE DATA must be stable before the active edge of the WRITE CLOCK WD hold time to WCLK: time the WRITE DATA must be stable after the active edge of the WRITE CLOCK WE setup time to WCLK: time the WRITE ENABLE must be stable before the active edge of the WRITE CLOCK WE hold time to WCLK: time the WRITE ENABLE must be stable after the active edge of the WRITE CLOCK WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the time when the data is available at RD Figure 25: RAM Cell Write Timing TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD Parameter Value Min. Max.
WCLK
WA
tSWA
WD
tHWA
tSWD
WEN
tHWD
tSWE
RD old data
tHWE
new data
tWCRD
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Table 31: RAM Cell Read Timing
Symbol tSRA tHRA tSRE tHRE tRCRD Parameter RA setup time to RCLK: time the READ ADDRESS must be stable before the active edge of the READ CLOCK RA hold time to RCLK: time the READ ADDRESS must be stable after the active edge of the READ CLOCK RE setup time to WCLK: time the READ ENABLE must be stable before the active edge of the READ CLOCK RE hold time to WCLK: time the READ ENABLE must be stable after the active edge of the READ CLOCK RCLK to RD: time between the active READ CLOCK edge and the time when the data is available at RD Figure 26: RAM Cell Read Timing Value Min. TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD
RCLK
RA
tSRA
RE
tHRA
tSRE
RD old data
tHRE
new data
tRCRD
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FIFO Timing
Figure 27: FIDO Module
DIN[x:0] PUSH Fifo_Push_Flush Push_Clk POP Fifo_Pop_Flush Pop_Clk
DOUT[x:0]
Almost_Full Almost_Empty PUSH_FLAG[3:0] POP_FLAG[3:0]
NOTE: x = {1,2,3,...35}.
Table 32: FIFO PUSH Timing Symbol tSPUSHD tHPUSHD tSPUSHEN tHPUSHEN tSPUSHFLUSH tHPUSHFLUSH tFPUSH tCOAF tCOPUSHFLAG Parameter WD setup time to Clk1: time WD must be stable before the active edge of the FIFO clock WD hold time to Clk1: time WD must be stable after the active edge of the FIFO clock WEN setup time to Clk1: time WEN must be stable before the active edge of the FIFO clock WEN hold time to Clk1: time WEN must be stable after the active edge of the FIFO clock FLUSH setup time to Clk1: time CS1 must be stable before the active edge of the FIFO clock FLUSH hold time to Clk1: time CS1 must be stable after the active edge of the FIFO clock Clk1 to Push: time between the active FIFO CLOCK edge and the time when the data is pushed to the FIFO Clock-to-out of Almost Full Clock-to-out of FIFO Push level indicator Value Min. TBD TBD TBD TBD TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD TBD TBD TBD
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Figure 28: FIFO PUSH Timing
Push_Clk
WD
tSPUSHD
PUSH
tHPUSHD
tSPUSHEN
tHPSUHEN
Fifo_Push_Flush
tSPUSH
FLUSH
tHPUSH
FLUSH
Almost_Full
tCOAF
PUSH_FLAG old status new status
tCOPUSHFLAG
Table 33: FIFO POP Timing Symbol tSPOPEN tHPOPEN tSPOPFLUSH tHPOPFLUSH tFPOP tCOPOP tCOAE tCOPOPFLAG Parameter POP setup time to Clk2: time POP must be stable before the active edge of the FIFO clock POP hold time to Clk2: time POP must be stable after the active edge of the FIFO clock FLUSH setup time to Clk2: time CS2 must be stable before the active edge of the FIFO clock FLUSH hold time to Clk2: time CS2 must be stable after the active edge of the FIFO clock Clk2 to Pop: time between the active FIFO CLOCK edge and the time when the data is popped from the FIFO Clock-to-out of RD Clock-to-out of Almost Empty Clock-to-out of FIFO Pop level indicator Value Min. TBD TBD TBD TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD TBD TBD
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Figure 29: FIFO POP Timing
Pop_Clk
POP
tSPOPEN
Fifo_Pop_Flush
tHPOPEN
tSPOP
FLUSH
tHPOP
FLUSH
RD
tCOPOP
Almost_Empty
tCOAE
POP_FLAG old status new status
tCOPOPFLAG
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GPIO Cell Timing
Figure 30: PolarPro I/O Cell Output Path
SLEW[1:0] P[3:0]
I/O PAD
OUTZ OUTRZ_EN D Q Slew Rate & Drive Strength Logic
OSEL
OEZ
D
Q
ESEL
INZ Q ISEL D FIXHOLD logic
INRZ_EN FIXHOLD RST CLK DI_EN
Figure 31: PolarPro I/O Cell Output Enable Timing
tOUTHL tOUTLH tPZL tPZH tPHZ tPLZ
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Table 34: PolarPro I/O Cell Output Timing Symbol Output Register Cell Only tOUTLH tOUTHL tPZH tPZL tPHZ tPLZ tCOP Output Delay low to high (90% of H) Output Delay high to low (10% of L) Output Delay tri-state to high (90% of H) Output Delay tri-state to low (10% of L) Output Delay high to tri-state Output Delay low to tri-state Clock-to-out delay (does not include clock tree delays) Parameter TBD TBD TBD TBD TBD TBD TBD Value (ns) Slow Slew Max Fast Slew Max TBD TBD TBD TBD TBD TBD TBD
Table 35: Output Slew Rates @ VCCIO = 3.3 V, T = 25 C
Fast Slew Rising Edge Falling Edge TBD TBD Slow Slew TBD TBD
Table 36: Output Slew Rates @ VCCIO = 2.5 V, T = 25 C
Fast Slew Rising Edge Falling Edge TBD TBD Slow Slew TBD TBD
Table 37: Output Slew Rates @ VCCIO = 1.8 V, T = 25 C
Fast Slew Rising Edge Falling Edge TBD TBD Slow Slew TBD TBD
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Figure 32: PolarPro I/O Cell Input Path
SLEW[1:0] P[3:0]
I/O PAD
OUTZ OUTRZ_EN D Q Slew Rate & Drive Strength Logic
OSEL
OEZ
D
Q
ESEL
INZ Q ISEL D FIXHOLD logic
INRZ_EN FIXHOLD RST CLK
Figure 33: PolarPro Input Register Cell Timing
RST
CLK
D
tISU
Q
tIHL tICO tIRST
E
tIESU
tIEH
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Table 38: I/O Input Register Cell Timing
Symbol tISU tIHL tICO tIRST tIESU tIEH Parameter Input register setup time: time the synchronous input of the flip-flop must be stable before the active clock edge Input register hold time: time the synchronous input of the flip-flop must be stable after the active clock edge Input register clock-to-out: time taken by the flip-flop to output after the active clock edge Input register reset delay: time between when the flip-flop is "reset" (low) and when the output is consequently "reset" (low) Input register clock enable setup time: time "enable" must be stable before the active clock edge Input register clock enable hold time: time "enable" must be stable after the active clock edge Value Min. TBD TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD
Table 39: I/O Input Buffer Delays
Parameter Symbol To get the total input delay add this delay to tISU tSID (LVTTL) tSID (LVCMOS2) tSID (LVCMOS18) tSID (GTL+) tSID (SSTL3) tSID (SSTL2) tSID (PCI) LVTTL input delay: Low Voltage TTL for 3.3 V applications LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications LVCMOS18 input delay: Low Voltage CMOS for 1.8 V applications GTL+ input delay: Gunning Transceiver Logic SSTL3 input delay: Stub Series Terminated Logic for 3.3 V SSTL2 input delay: Stub Series Terminated Logic for 2.5 V PCI input delay: Peripheral Component Interconnect for 3.3 V Min. TBD TBD TBD TBD TBD TBD TBD Max. TBD TBD TBD TBD TBD TBD TBD Value
DDR Cell Timing
TBD
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Package Thermal Characteristics
The PolarPro device is available for Commercial (0C to 85C Junction), Industrial (-40C to 100C Junction), and Military (-55C to 125C Junction) temperature ranges. Thermal Resistance Equations:
JC = (TJ - TC)/P JA = (TJ - TA)/P
PMAX = (TJMAX - TAMAX)/JA Parameter Description:
JC: Junction-to-case thermal resistance JA: Junction-to-ambient thermal resistance
TJ: Junction temperature TA: Ambient temperature P: Power dissipated by the device while operating PMAX: The maximum power dissipation for the device TJMAX: Maximum junction temperature TAMAX: Maximum ambient temperature NOTE: Maximum junction temperature (TJMAX) is 125C. To calculate the maximum power dissipation for a device package look up JA from Table 40, pick an appropriate TAMAX and use: PMAX = (125C - TAMAX)/
JA
Table 40: Package Thermal Characteristics
Device QL1P1000 QL1P600 QL1P300 QL1P150
Package Description Package Code Package Type PS PS PS PS PS PS PS PS PF PT PS PF LBGA LBGA LBGA LBGA LBGA LBGA LBGA LBGA TQFP TFBGA LBGA TQFP TFBGA LBGA Pin Count 256 324 256 324 256 324 256 324 144 196 256 144 196 256 0 LFM TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
JA ( C/W)
200 LFM TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD 400 LFM TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD TBD
QL1P100
QL1P075
PT PS
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Table 41: Maximum Junction and Maximum Body Temperature Package Type TFBGA TQFP LBGA TFBGA - Pb-free TQFP - Pb-free LBGA - Pb-free
JA (C)
TBD TBD TBD TBD TBD TBD
Tbody (C) TBD TBD TBD TBD TBD TBD
Moisture Sensitivity Level
All PolarPro devices are Moisture Sensitivity Level 3.
Table 42: Solder and Lead Finish Composition Lead Included BGA Solder QFP Lead Finish 73% Pb, 37% Sn 85% Pb, 15% Sn Lead-free Sn3AgCu:Sn4AgCua Sn (matte)
a. Sn3AgCu:Sn4AgCu means that Ag can range from 3% to 4%. Cu is always 0.5%.
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Power Vs. Operating Frequency
The basic power equation which best models power consumption is given below: PTOTAL = 0.350 + f[0.0031 LC + 0.0948 CKBF + 0.01 CLBF + 0.0263 0.543 RAM + 0.20 PLL + 0.0035 INP + 0.0257 OUTP] (mW) Where:
CKLD +
LC = number of logic cells in the design CKBF = number of clock buffers CLBF = number of column clock buffers CKLD = number of loads connected to the column clock buffers RAM = number of RAM blocks PLL = number of PLLs INP = number of input pins OUTP = number of output pins
NOTE: To learn more about power consumption, see QuickLogic Application Note 60 at
http://www.quicklogic.com/images/appnote60.pdf.
Power-Up Sequencing
Figure 34: Power-Up Sequencing
VCCIO |VCCIO - VCC| MAX
Voltage
VCC
VCC
'N' us
Time
NOTE: Power-up sequencing timing will be provided once production silicon characterization is completed.
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Pin Descriptions
Table 43: Pin Descriptions Pin Direction Function Dedicated Pin Descriptions The I/O pin is a bi-directional pin, configurable to either an input-only, output-only, or bi-directional pin. The letter inside the parenthesis means that the I/O is located in the bank with that letter. If an I/O is not used, the development software provides the option of tying that pin to GND, VCCIO, or Hi-Z. This pin provides access to a distributed network capable of driving the CLOCK, SET, RESET, all inputs to the Logic Cell, READ and WRITE CLOCKS, Read and Write Enables of the Embedded RAM Blocks, and I/O inputs. The voltage tolerance of this pin is specified by VCCIO. Input clock for CCM. The voltage tolerance for this pin is specified by the VCCIO of the same bank. CCM input voltage level. Configurable as 1.8 V only. If CCMVCC is grounded, then the CCM is disabled. Connect to ground. Active low. Therefore, when VLP pin is low, the device will go into low power mode. Tie VLP to 3.3 V to disable low power mode. Connect to 1.8 V supply. This pin provides the flexibility to interface the device with either a 3.3 V, 2.5 V, or 1.8 V device. The letter inside the parenthesis means that the VCCIO is located in the bank with that letter. Every I/O pin in the same bank will be tolerant of the same VCCIO input signals and will drive VCCIO level output signals. This pin must be connected to either 3.3 V, 2.5 V, or 1.8 V. Connect to ground. The D inside the parenthesis means that the I/O is located in Bank D. If an I/O is not used, the development software provides the option of typing that pin to GND, VCCIO, or Hi-Z. The D inside the parenthesis means that the I/O is located in Bank D. If an I/O is not used, the development software provides the option of typing that pin to GND, VCCIO, or Hi-Z. The D inside the parenthesis means that the I/O is located in Bank D. If an I/O is not used, the development software provides the option of typing that pin to GND, VCCIO, or Hi-Z. Description
GPIO(C:A)
I/O
General purpose input/output pin
CLK(D:A)
I
Global clock network pin low skew global clock
CCMIN(1:0) CCMVCC (1:0) CCMGND(1:0) VLP VCC
I I I I I
CCM clock input Power supply pin for CCM Ground pin for CCM Voltage low power Power supply pin
VCCIO(D:A)
I
Input voltage tolerance pin
GND DQ/ GPIO(D)
I
Ground pin Configurable pin can be declared as either a DDRIO DQ or as a general purpose I/O Configurable pin can be declared as either a DDRIO DQS or as a general purpose I/O Configurable pin can be declared as either a DDRIO DQ, DDR negative clock, or as a general purpose I/O.
I/O
DQS/ GPIO(D)
I/O
DQCK_N/ GPIO(D)
I/O
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Table 43: Pin Descriptions (Continued) Pin DQCK_P/ GPIO(D) Direction Function Configurable pin can be declared as either a DDRIO DQ, DDR positive clock, or as a general purpose I/O. Differential reference voltage Description The D inside the parenthesis means that the I/O is located in Bank D. If an I/O is not used, the development software provides the option of typing that pin to GND, VCCIO, or Hi-Z. The INREF is the reference voltage pin for the SSTL1.8 and SSTL2 standards. The D inside the parenthesis means that INREF is located in Bank D. Tie this pin to GND if voltage referenced standards are not used. Active high reset used during power-up sequence. Drive to VCCIO(B) during power-up. Pull low after power-up to begin normal operation. JTAG Pin Descriptions TDI/RSI I Test data in for JTAG/RAM init. serial data in Active low reset for JTAG Hold HIGH during normal operation. Connect to VCCIO(B) if unused. Hold LOW during normal operation. Connect to GND if unused. During JTAG, a high voltage is based on VCCIO(B). Hold HIGH during normal operation. Connect to VCCIO(B) if not used for JTAG. Hold HIGH or LOW during normal operation. Connect to VCCIO(B) or GND if not used for JTAG. Must be left unconnected if not used for JTAG. The output voltage drive is specified by VCCIO(B).
I/O
VREF(D)
I
POR
I
Power-on reset
TRSTB
I
TMS TCK TDO
I I O
Test mode select for JTAG Test clock for JTAG Test data out for JTAG
Recommended Unused Pin Terminations for PolarPro Devices
All unused, general purpose I/O pins can be tied to VCC, GND, or Hi-Z (high impedance) internally. Terminate the rest of the pins at the board level as recommended in Table 44.
Table 44: Recommended Unused Pin Terminations Signal Name VREF CLK a VLP TDI TRSTB TMS TCK TDO Recommended Termination If an I/O bank does not require the use of the INREF signal, connect the pin to GND. Connect to GND or VCCIO(x) if unused. Tie VLP to 3.3 V to disable low power mode. Connect to VCCIO(B) if not used for JTAG. Connect to GND if not used for JTAG. Connect to VCCIO(B) if not used for JTAG Connect to VCCIO(B) or GND if not used for JTAG. Must be left unconnected if not used for JTAG.
a. x represents A, B, C or D.
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Packaging Pinout Diagrams and Tables
PolarPro QL1Pxxx - 144 TQFP Pinout Diagram
Pin 1 Pin 109
PolarPro QL1Pxxx-7PF144C
Pin 37
Pin 73
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PolarPro QL1Pxxx - 144 TQFP Pinout Table
Table 45: QL1P050 - 144 TQFP Pinout Table
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Function VCCIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) VCC GPIO(C) GPIO(C) VCC GPIO(C) GPIO(C) VCCIO(C) GPIO(C) GPIO(C) GPIO(C) CLK(C) TCK GPIO(C) GPIO(C) VCCIO(B) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) VCCIO(C) GND GND Pin 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 Function GND GPIO(B) GPIO(B) TDO VCCIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) TDI CLK(B) VCCIO(B) VCC CLK(B) GPIO(B) VCC GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) VCCIO(B) VLP POR GND Pin 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Function VCCIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) VCC GPIO(A) TRSTB GPIO(A) GPIO(A) CLK(A)/CCMIN(1) GPIO(A) VCCIO(A) GPIO(A) GPIO(A) GPIO(A) VCC GPIO(A) GPIO(A) VCC GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) CCMVCC(1) VCCIO(A) CCMGND(1) GND GND Pin 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Function VCCIO(D) VREF(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQCK_N/GPIO(D) DQCK_P/GPIO(D) DQS/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) TMS DQ/GPIO(D) DQ/GPIO(D) VCC CLK(D) VCCIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQCK_N/GPIO(D) DQCK_P/GPIO(D) DQS/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) VREF(D) DQ/GPIO(D) VCCIO(D) VCC VCCIO(D) GND GND
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PolarPro QL1Pxxx - 256 LBGA Pinout Diagram
Top
PolarPro QL1Pxxx-7PS256C
Bottom
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PolarPro QL1Pxxx - 256 LBGA Pinout Table
Table 46: QL1P050 - 256 LBGA Pinout Table
Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 Function GND DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQS/GPIO(D) DQ/GPIO(D) CLK(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) GPIO(A) GND DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQCK/GPIO(D) DQCK/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQS/GPIO(D) GPIO(C) GPIO(C) GND DQ/GPIO(D) DQCK/GPIO(D) DQCK/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQCK/GPIO(D) DQ/GPIO(D) Pin C12 C13 C14 C15 C16 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15 E16 F1 F2 F3 F4 F5 F6 Function DQCK/GPIO(D) DQCK/GPIO(D) GND DQ/GPIO(D) DQ/GPIO(D) GPIO(C) GPIO(C) GPIO(C) GPIO(C) VREF(D) DQS/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQ/GPIO(D) DQCK/GPIO(D) DQ/GPIO(D) VREF(D) DQ/GPIO(D) GPIO(A) GPIO(A) GPIO(A) GPIO(C) GPIO(C) GPIO(C) GPIO(C) CCMGND(0) VCCIO(D) VCCIO(D) VCCIO(D) VCCIO(D) VCCIO(D) VCCIO(D) CCMGND(1) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(C) GPIO(C) GPIO(C) GPIO(C) CCMVCC(0) VCC Pin F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 G12 G13 G14 G15 G16 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 J1 Function VCC GND TMS VCC DQ/GPIO(D) CCMVCC(1) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) VCC GND GND GND GND VCC GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) CLK(C)/ CCMIN(0) GPIO(C) GPIO(C) GPIO(C) VCCIO(C) TCK GND VCC VCC GND GND VCCIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(C) Pin J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 J12 J13 J14 J15 J16 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 L12 Function GPIO(C) GPIO(C) GPIO(C) VCCIO(C) GND GND VCC VCC GND TRSTB VCCIO(A) GPIO(A) GPIO(A) GPIO(A) CLK(A) CCMIN(1) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) VCC GND GND GND GND VCC GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(C) GPIO(C) GPIO(C) GPIO(C) GPIO(C) STM VCC TDI POR VCC VCCIO(B) VLP Pin L13 L14 L15 L16 M1 M2 M3 M4 M5 M6 M7 M8 M9 M10 M11 M12 M13 M14 M15 M16 N1 N2 N3 N4 N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 P1 P2 P3 P4 P5 P6 P7 Function GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(C) GPIO(C) GPIO(B) GPIO(B) GPIO(B) VCCIO(B) VCCIO(B) VCCIO(B) VCCIO(B) VCCIO(B) VCCIO(B) GPIO(B) GPIO(A) GPIO(A) GPIO(A) GPIO(A) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(A) GPIO(B) GPIO(B) GPIO(B) GND GPIO(B) GPIO(B) GPIO(B) GPIO(B) Pin P8 P9 P10 P11 P12 P13 P14 P15 P16 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 Function GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GND GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) TDO GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GND GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) CLK(B) GPIO(B) CLK(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GPIO(B) GND
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Package Mechanical Drawings
144 TQFP Packaging Drawing
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9.
H
*
DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08mm TOTAL IN EXCESS OF THE b DIMENSION AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. 10. CONTROLLING DIMENSION: MILLIMETER. 11. MAXIMUM ALLOWABLE DIE THICKNESS TO BE ASSEMBLED IN THIS PACKAGE FAMILY IS 0.38 MILLIMETERS. 12. THIS OUTLINE CONFORMS TO JEDEC PUBLICATION 95 REGISTRATION MO-136, VARIATION BT.
G F
12
11
NOTES:
H
1. ALL DIMENSIONING AND TOLERANCING CONFORM TO ANSI Y14.5-1982. 2. DATUM PLANE -H- LOCATED AT MOLD PARTING LINE AND COINCIDENT WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE. 3. DATUMS A-B AND -D- TO BE DETERMINED AT CENTERLINE BETWEEN LEADS WHERE LEADS EXIT PLASTIC BODY AT DATUM PLANE -H- . 4. TO BE DETERMINED AT SEATING PLANE -C- .
G
5. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE MOLD PROTRUSION IS 0.254 MM ON D1 AND E1 DIMENSIONS. 6. "N" IS THE TOTAL NUMBER OF TERMINALS. 7. THESE DIMENSIONS TO BE DETERMINED AT DATUM PLANE -H- . 8. THE TOP OF PACKAGE IS SMALLER THAN THE BOTTOM OF PACKAGE BY 0.15 MILLIMETERS, AND THE TOP OF THE PACKAGE WILL NOT OVERHANG THE BOTTOM OF THE PACKAGE.
F
(JEDEC VARIATION)
ALL DIMENSIONS IN MILLIMETERS
QuickLogic PolarProTM Data Sheet Rev. A
E
S Y M B O L
BT MIN. 1.60 0.05 1.35 22.00 BSC.
4 7,8 4 7,8
NOM.
MAX.
N O T E
E
A A1 A2 D D1 E E
1
0.10 1.40 20.00 BSC. 22.00 BSC. 20.00 BSC. 1.45
0.15
D
D
C
C
144 TQFP Packaging Drawing (Continued)
L M N e b b1 ccc ddd
* NOTE: THE 128 LEAD IS A COMPLIANT DEPOPULATION OF THE 144 LEAD MO-136 VARIATION BT.
0.45 0.14 *128, 144 0.50 BSC. 0.17 0.17 0.20 0.22 0.27 0.23 0.08 0.08
0.60
0.75
PRELIMINARY
9
10 9 8 7 6 5 4 3
B
B
A
A
S IZ E
DWG. NO.
R EV .
A1
SCALE
03-016-11
6/1
2
SHEET
C 2 of 2
1
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256 LBGA Package Drawing
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256 LBGA Package Drawing (Continued)
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Packaging Information
The PolarPro product family packaging information is presented in Table 47. Table 47: Packaging Options
Device Device Information QL1P075 / QL1P100 Pin 144 TQFP Package Definitionsa 196 TFBGA 256 LBGA Pitch 0.50 mm 0.80 mm 1.0 mm 256 LBGA 324 LBGA 1.0 mm 1.0 mm QL1P150 / QL1P300 / QL1P600 / QL1P1000 Pin Pitch
a. TFBGA = Thin Profile Fine Pitch Ball Grid Array LBGA = Low Profile Ball Grid Array TQFP = Thin Quad Flat Pack
Ordering Information
QL 1P075 -6 PF144 C
Operating Range: C = Commercial I = Industrial M = Military Package Lead Count: PF144 (PFN144)* = 144-pin TQFP (0.5 mm) PT196 (PTN196)* = 196-pin TFBGA (0.8 mm) Speed Grade: PS256 (PSN256)* = 256-pin LBGA (1.0 mm) PS324 (PSN324)* = 324-pin LBGA (1.0 mm) -6 - fast Part Number: -7 - faster 1P075 -8 - fastest 1P100 QuickLogic Device 1P150 1P300 1P600 1P1000
* Lead-free packaging is available, contact QuickLogic regarding availability (see Contact Information).
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Contact Information
Phone: (408) 990-4000 (US) (905) 940-4149 (Canada) +(44) 1932 57 9011 (Europe - except Germany/Benelux) +(49) 89 930 86 170 (Germany/Benelux) +(86) 21 6867 0273 (Asia - except Japan) +(81) 45 470 5525 (Japan) E-mail: Sales: info@quicklogic.com www.quicklogic.com/sales
Support: www.quicklogic.com/support Internet: www.quicklogic.com
Revision History
Revision A Date November 2005 Originator and Comments Jason Lew and Kathleen Murchek First release
Copyright and Trademark Information
Copyright (c) 2005 QuickLogic Corporation. All Rights Reserved. The information contained in this document is protected by copyright. All rights are reserved by QuickLogic Corporation. QuickLogic Corporation reserves the right to modify this document without any obligation to notify any person or entity of such revision. Copying, duplicating, selling, or otherwise distributing any part of this product without the prior written consent of an authorized representative of QuickLogic is prohibited. QuickLogic and the QuickLogic logo, and QuickWorks are registered trademarks of QuickLogic Corporation; PolarPro and SpDE are trademarks of QuickLogic Corporation.
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